In ECL (emittor coupled logic) transistor never goes into saturation coz it has CML (current mode logic) with negative voltage.
advantages: 1.noise free
2. high speed(400MHz)
3. clock tree generation logic
disadvantages:1.more power consumption
advantages: 1.noise free
2. high speed(400MHz)
3. clock tree generation logic
disadvantages:1.more power consumption
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